WEBINAR

Optimizing the performance and portability of multicore DSP platforms
with a scalable programming model supporting the Multicore Association®’s MCAPI®


- Presented: June 26, 2012

- View Webinar Powerpoint Slides (PDF): Click to View

Overview

The demand for increased application performance and the evolving nature of multicore DSP capabilities, poses challenges to developers’ realizing the full potential of multicore platforms while still maintaining future portability and scalability. This webinar will examine some of these challenges and present a solution that exists today for achieving full multicore entitlement. Specifically, the presenters will demonstrate how to ‘instantly’ apply MCAPI to a flexible system design, utilizing a graphical user interface to simplify and visualize the topology and inter-process communication strategy.

 

Presenters

Debbie Greenstreet

  • Strategic marketing director, TI multicore processors business
  • 20+ years in telecommunications market
  • Pioneer and evangelist in VoIP industry

Sven Brehmer

  • CEO and founder PolyCore Software
  • MCA Board member
  • Chairman of MCAPI® working group
  • Significant contributor on MRAPI® specification

 

Moderator

Markus Levy

  • President of Multicore Association®
  • Chairman of Multicore Developer Conference
  • Founder and President of EEMBC

 


Texas Instruments

Texas Instruments’ KeyStone multicore architecture is the platform for true multicore innovation, offering developers a robust portfolio of high performance, low-power multicore devices. Unleashing breakthrough performance, the KeyStone architecture is the foundation upon which TI’s new TMS320C66x DSP generation was developed, and has the capacity to provide full processing capability to every core in a multicore device. KeyStone devices are optimized for many high performance markets including wireless base stations, mission critical, test and automation, medical imaging and high performance computing.

Polycore Software

With the Poly-Platform programming model, designers are able to quickly and easily model and implement the communication infrastructure, and have the ability to make rapid adjustments toward an optimized design. Data sharing is abstracted, and hardware accelerators are easily configured, simplifying the programming process as other layers in the design change. Applications can be streamlined for high performance multicore processors, and are ready to transition to next generation architectures.