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MULTICORE RESOURCE MANAGEMENT API WORKING GROUP

Objective
To define an industry-standard API that specifies essential application-level resource management capabilities. Multicore applications require this API to allow coordinated concurrent access to system resources in situations where: (1) there are not enough resources to dedicate to individual tasks or processors, and/or (2) the runtime system does not provide a uniformly accessible mechanism for coordinating resource sharing.

This API will be applicable to both SMP and AMP embedded multicore implementations (whereby AMP refers to heterogeneous both in terms of software and hardware).


Overview
The purpose of the Multicore Resource Management API (MRAPI) is to capture the essential capabilities required for managing shared resources in a closely distributed (multiple cores on a chip and/or chips on a board) embedded system. These resources include multiple cores or chips, hardware accelerators, memory regions, and I/O. MRAPI will support the ability to declare and allocate/destroy shared memory regions and to identify nodes which have access to each region. MRAPI will also provide application-level synchronization primitives for coordinating access to shared resources.
Additional features may include resource registration and locking facilities which would allow the user to register a globally visible named entity and request and release locks against it. The MRAPI working group will work in close collaboration with the MCAPI working group and the Hypervisor working group to ensure that MRAPI supports critical usage scenarios for communications and virtualization.

Status
The newly-established Multicore Resources Management working group holds regularly scheduled phone meetings (typically bi-weekly). The group plans to have a first draft ready by November, followed by a three-month review and revision period. Although the end product of this working group will probably be publicly available, we encourage you to join the Multicore Association to participate in the discussion and development phases of this project.

Chairperson

Jim Holt, Ph.D., Manager, Processor Core Architecture and Modeling Team, Networking and Multimedia group, Freescale Semiconductor.


 

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