SOFTWARE-HARDWARE INTERFACE FOR MULTI-MANY-CORE (SHIM™)
The primary goal of the SHIM working group is to define an architecture description standard from the software design perspective – this will provide a common interface that will abstract the hardware properties that are critical to enable multicore tools.
Multicore and manycore development tool vendors and runtime systems cannot possibly support the virtually unlimited number of processor configurations. The lack of quality and portable tools has kept system developers from fully utilizing the various multicore and manycore devices. Ultimately, SHIM will promote highly-optimized tools that can provide efficient utilization of very complex SoCs and potentially eliminate the need for users to comprehend 1000-page manuals to program all the device features.
Unlike the IEEE IP-XACT standard which defines and describes electronic components for hardware design, the primary goal of the SHIM working group is to define an architecture description standard from the software design perspective. For example, some of the architectural features that can be (directly or indirectly) described are the processor cores, the inter-core communication channels (in support of message passing protocols such as the Multicore Association’s MCAPI), the memory system (including hierarchy, topology, coherency, memory size, latency), the network-on-chip (NoC) and routing protocol, and hardware virtualization features. Furthermore, SHIM could be very aligned with the work already being done by the Multicore Association’s Tools Infrastructure Working Group (TIWG).
The SHIM standard will allow vendor-specific, non-standard architectural information for customized tools. While the SHIM standard itself will be publicly available, the vendor-specific information can remain confidential between a processor vendor and its development tool partners.
Examples of the applicability of the SHIM standard:
- Performance information is critical for most software development tools such as performance analysis tools, auto-parallelizing compilers, and other parallelizing tools.
- System configuration to provide basic architectural information for operating systems, middleware, and other runtime libraries
- Hardware modeling to support processor simulation and architecture exploration.
The SHIM worgroup holds regularly scheduled meetings, typically via web-meeting. Although the end product of this working group will be publicly available, we encourage you to join the Multicore Association to participate in the discussion, development, and feedback phases of this project. The working group expects to complete the first SHIM specification in 2014.
- Masaki Gondo, CTO, eSOL
Primary Contributing Members
Cavium Networks, CriticalBlue, eSOL, Freescale, Nagoya University, PolyCore Software, Renesas, Texas Instruments, TOPS Systems, Vector Fabrics, and Wind River.