From Markus Levy
The Multicore Association®
- Launch of New Working Group: SHIM
- New MCA Members
- Multicore Survey
- Multicore DevCon 2013 Proceedings
- MCA Youtube Channel
- Multicore Programming Program at SJSU
- Upcoming Event
Launch of New MCA Working Group: SHIM
Most will recognize that a SHIM is a spacer. But for the MCA, SHIM is the Software-Hardware Interface for Multi-Many Core (SHIM), and it will provide a common interface to abstract the hardware properties that matter to multicore tools. These hardware properties include the processor cores, the inter-core communication channels (in support of message passing protocols such as the Multicore Association’s MCAPI), the memory system (including hierarchy, topology, coherency, memory size, latency), the network-on-chip (NoC) and routing protocol, hardware virtualization features, and more.
The Multicore Association’s SHIM standard will be beneficial for many types of tools, including performance estimation, system configuration, and hardware modeling. Masaki Gondo, Software CTO and GM of Technology at eSOL, volunteered to chair the SHIM Working Group within the Multicore Association. Currently, the member companies participating in the SHIM WG include Cavium, CriticalBlue, eSOL, Freescale Semiconductor, Mentor Graphics, Nagoya University, Nokia Siemens Networks, PolyCore Software, Renesas Electronics, Texas Instruments, TOPS Systems, Vector Fabrics, Wind River, and Xilinx. Learn more about SHIM.
New MCA Members
We’ve recently added a host of new members to help drive our future standards. Renesas Electronics’ has joined as a new Board Member. eSOL, an MCA working group member since 2007, has recently upgraded to a Board Member. TOPS Systems of Japan has joined as a working group member. Vector Fabrics, based in the Netherlands, has also joined as a working group member. And last, but not least, Nagoya University has joined our membership.
The members of the Multicore Association always want to make sure that we are providing you with the tools that will better support your multicore system and software development. If you haven’t taken it yet, we would greatly appreciate your input on this very short survey.
We’ll make the results anonymous and present them to you in the next newsletter.
Multicore Developers Conference Proceedings
If you missed the Multicore Developers Conference, you can obtain the proceedings for $139. It includes several presentations related to Multicore Association including “How Operating Systems and Tools Will Face the Many Software Challenges of Manycore”, “Software RULES the World”, “Multicore Software Development Practices for Embedded Systems”, and “Using MCA Interfaces to Enable High-Level Programming for Embedded Systems”
Also, mark your calendar for the 9th annual Multicore Developers Conference, taking place May 7-8, 2014 in Santa Clara, CA.
MCA on Youtube
We have created a YouTube channel that serve as the place to go for all our videos and webinars. Check out our latest, providing an introduction to SHIM - Software-Hardware Interface For Multi-Many-Core. http://www.youtube.com/user/multiassoc
Multicore Programming Program at San Jose State University
Beginning in Fall 2013, San Jose State University will offer a multi-semester program to provide the students with the knowledge and design experience of multicore architectures and programming. More specifically, the sessions will familiarize students with multicore architectures (such as private and shared cache architecture, inter-core communication), understand the concepts of parallel computing, and master parallel programming techniques, and more. Check out the details.
At ESWeek on October 3, there will be a workshop aiming to bring together experts from academia and industry to present, discuss and explore the latest state-of-the-art academic and industrial innovations that contribute to the advancement of many-core embedded systems. Speakers will include Masaki Gondo of eSOL, and he will present “The use of task priority for assuring hard real-time tasks and load-balancing soft real-time tasks at the same time on manycore architectures.”